This invention relates to electronic circuit design and implementation, and more particularly to partitioning an electronic circuit design into subcircuits such that the requirements for connections between the subcircuits are reduced.
Although this invention is applicable in many other contexts, the significance of the invention will be fully appreciated from the following discussion, which is primarily directed to application of the invention to sub-dividing a user's logic design into subcircuits that can be implemented in respective regions of programmable logic in a programmable logic array integrated circuit device, the subcircuits being selected to hold down the number of connections that must be made between the logic regions. Examples of other possible uses of the invention are partitioning any type of circuitry among two or more components such as printed circuit boards or integrated circuits.
Programmable logic array integrated circuit devices typically have a large number of regions of programmable logic. An example of such a device is shown in commonly assigned Cliff et al. U.S. Pat. No. 5,689,195, which is hereby incorporated by reference herein. Each logic region is programmable to perform any of a plurality of logic functions on a plurality of input signals applied to the region to produce one or more output signals of the region. A programmable network of interconnection conductors is also provided on the device. This network is programmable to connect each logic region output to substantially any logic region input so that much more complicated logic functions can be performed by concatenating the functions of the individual logic regions. The interconnection conductor network is also used to bring external signals into the logic of the device and to convey signals generated by the device out for external use.
An objective in the design of programmable logic array integrated circuit devices is to provide enough interconnection circuitry so that needed interconnections can be made for the largest possible number of users' logic designs, without providing excessive amounts of such resources that take up space and will be largely unused in many cases. Programmable logic array integrated circuits are therefore typically designed with substantially less interconnection circuitry than would be required for completely universal, simultaneous connectability of any logic region output to any logic region input.
A technology which can be employed to help hold down the need to use interconnection resources in programmable logic array devices is circuit partitioning. In this application of circuit partitioning the objective is to partition the user's logic design into a number of logic design subcircuits, each of which will fit in a logic region, these subcircuits being additionally selected to hold down the required number of connections between subcircuits. Efficient partitioning of this kind may make it possible to implement in a programmable logic array device a user's logic design that otherwise would not be implementable in that device because of premature exhaustion of the interconnection resources of the device. Another advantage of the availability of efficient partitioning is that it may make it possible to design programmable logic array devices with an even smaller percentage of the overall resources of the device devoted to interconnections, without adversely affecting usability of the device, and possibly even increasing usability by allowing more logic regions to be added in the area that otherwise would be devoted to interconnection resources.
Even if partitioning is being performed for purposes other than fitting a user's logic design into a programmable logic array device, holding down the number of connections between the subcircuits into which a circuit must be partitioned is frequently an important objective of the partitioning. For example, if a circuit design is being partitioned so that it can be divided among two or more circuit boards or integrated circuits, it is generally desirable to reduce the number of connections that will be needed between the circuit boards or integrated circuits. In the case of integrated circuits, for example, there may simply not be enough input/output pin space available on an integrated circuit unless efforts are made to reduce the required number of connections to and from the device.
Many circuit partitioning techniques are known (see, for example, the techniques discussed in Mendel U.S. Pat. No. 5,341,308 and in Tse et al. U.S. Pat. No. 5,659,717, both of which are hereby incorporated by reference herein). Most partitioning techniques work by examining several possible partitions, and selecting the best of those solutions. Even the best solution selected by such a technique may be far from the truly optimal solution, but the computational expense of continuing the search for better solutions through vast numbers of possible solutions may be too great to warrant continuing the searching process. The above-described benefits of finding better partitions are considerable, however, and so there is a need for improved circuit partitioning techniques, especially those that avoid continued "brute force" searching through myriad possible solutions.
In view of the foregoing, it is an object of this invention to provide improved circuit partitioning techniques.
It is a more particular object of this invention to provide circuit partitioning techniques that improve upon the results of trial partitioning without continuing to simply search for more trial partitions in the same way that the initial trial partitions were found.